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VLSI System Verilog

VLSI System Verilog


System Verilog combines HDLS and the hardware verification language. It takes an object-oriented programming approach. It also teaches how to code in a System Verilog language-which is the most popular Hardware Description Language (HDL) used for SoC design and verification in semiconductor industry.

vlsi system


  • Pre- defined and User defined data types
  • Array types (Static, dynamic, associative)
  • 0OPS programming concepts (Eg: Class, Inheritance)
  • Constrained random stimulus generation
  • Casting (Static & dynamic)
  • SV Schedulers
  • Inter Process communication (Semaphore, mailbox)
  • Coverage Analysis (Code, Functional, FSM)
  • Interfaces and clocking block
  • Test bench creation using system Verilog concepts

system verilog

Duration: 48 hours

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