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Arut Jothi Towers

VLSI Verilog

VLSI Verilog

OBJECTIVE:

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. The course aims to provide thorough understanding of the fundamental concepts and design of VLSI systems. It includes digital circuit design process, design methodologies of VLSI systems, creation of the HDL code according to the given specification and also performing verification and implementation on FPGA kit.

vlsi verilog

COURSE CURRICULUM:

  • Introduction to VLSI Design Flow
  • Introduction to Linux platform and commands used
  • Library creation
  • Overview on designing of Digital circuit
  • Switch, Structural, Data Flow, Gate level and Behavioral Modelling 
  • Test Bench Creation
  • Design Compilation ,Elaboration, & Simulation.
  • Terminal and GUI mode simulation
  • ALU Design and Verification
  • Combinational UDP and Sequential UDP
  • Functions and task
  • Types of process: fork-join
  • Introduction to the pin configuration and Architecture of FPGA
  • Interfacing Input/output devices with FPGA
  • Pin planning using plan-ahead window
  • Design Verification using FPGA

VLSI System Verilog

Duration: 72 hours

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